Click here for EDACafe
Search:  
Click here for IBSystems
  Home | EDA Weekly | Companies | Downloads | e-Catalog | IP | Audio | Forums | News | Resources |
  Check Email | Submit Material | Universities | Books | Events | Advertise | PCBCafe| Subscription | techjobscafe |  ItZnewz  |  RSS  |
ChipScope™ Pro
www.mentor.com/dft
www.mentor.com/dsm
 EDACafe EDA Portal, EDA News, EDA Jobs, EDA Presentations, EDA Newsgroups, Electronic Design Automation.
Review the article and give us your feedbackeMail Article to a friend Printer Friendly version of the Article

Siemens Expands Its Use of Cadence Incisive Formal Verifier to Improve Time to Market



Rate This Article
Excellent
Good
Average
Bad
Poor
SAN JOSE, CA -- (MARKET WIRE) -- Jul 31, 2006 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Siemens has expanded its deployment of the Cadence® Incisive® Formal Verifier into its design flow for assertion-based formal analysis. Using Incisive Formal Verifier, Siemens experienced improvements in verification efficiency and reduced risks related to functional quality of complex designs.

"Cadence has brought early design formal analysis to the designer," said Ulrich Fuchs, ASIC Manager, Siemens Automation & Drives. "We have fully adopted and are expanding our usage of Incisive Formal Verifier improving our overall design and verification process."

Part of the Incisive Design Team family, Incisive Formal Verifier provides a more efficient way to perform block-level designer verification and close the loop on last-minute iterations with high confidence of producing a successful design. The technology can quickly expose most functional bugs during the early phases of the design process, including complex corner-case design bugs, and it can further validate proper design fixes.

"Broad production-flow deployments of Incisive Formal Verifier are becoming common-place in leading companies, and we are pleased to count Siemens among them," said Moshe Gavrielov, executive vice president and general manager, Verification Division, Cadence Design Systems, Inc.

Launched in May 2005, Incisive Formal Verifier has been used in production flows worldwide for competitive markets in consumer, communications, computer, networking, graphics and system-on-chip (SoC) designs. Design and verification engineers can verify design blocks months prior to testbench simulation, resulting in faster, more cost-efficient overall chip design and verification.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, and Incisive are registered trademarks of Cadence Design Systems in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Wendy Hynes
Text 100 for Cadence Design Systems, Inc.
415-593-8444
Email Contact





Review ArticleBe the first to review this article
www.mentor.com/dsm
www.mentor.com/pcb
NEW EDA DISCUSSION BOARDS!
Discuss Verilog!

CLICK HERE


Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc.
1-888-44-WEB-44 --- Contact us, or visit our other sites:
AECCafe  DCCCafe  TechJobsCafe  GISCafe  MCADCafe  NanoTechCafe  PCBCafe  
  Privacy Policy